1. Technical Field
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device and a method of driving the same capable of reducing a consumed current and of reducing the generation of heat in an integrated circuit.
2. Description of the Related Art
Recently, liquid crystal display (LCD) devices are more widely used in a variety of electronic products because of their features such as lightweight, slimness, low power consumption and so on. According to such a trend, the liquid crystal display devices have been used in office automation equipment, audio and video equipment and so on. Such a liquid crystal display device controls a light transmittance in accordance with a signal applied to a plurality of switching devices arranged in a matrix to display desired pictures on a screen. A thin film transistor (TFT) are mainly employed for the switching devices.
FIG. 1 shows a related art liquid crystal display device. As shown in FIG. 1, the related art liquid crystal display device includes a liquid crystal display panel 14 in which data lines D1 to Dm cross gate lines G1 to Gn, respectively, and a TFT is arranged at each crossing part for driving a liquid crystal cell Clc. A data driving circuit 12 supplies a video signal to the data lines D1 to Dm of the liquid crystal display panel 14. A gate driving circuit 13 supplies a scanning pulse to the gate lines G1 to Gn of the liquid crystal display panel 14. A timing controller 11 controls the data driving circuit 12 and the gate driving circuit 13.
The liquid crystal panel 14 has liquid crystals injected between two glass substrates, i.e., upper and lower glass substrates. The data lines D1 to Dm and the gate lines G1 to Gn are formed to cross each other perpendicularly and are formed together on the lower glass substrate. The TFT arranged at each crossing part of the data lines D1 to Dm and the gate lines G1 to Gn may provide video signals on the data lines D1 to Dm to the liquid crystal cell Clc in response to scanning pulses from the gate lines G1 to Gn. A gate electrode of the TFT is connected to the gate lines G1 to Gn, and a source electrode of the TFT is connected to the data lines D1 to Dm. Further a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc. A common voltage Vcom is supplied to a common electrode facing the pixel electrode. Further, the liquid crystal cell Clc of the liquid crystal display panel 14 is provided with a storage capacitor Cst for fixedly sustaining a voltage charged in the liquid crystal cell Clc. The storage capacitor Cst may be provided between a liquid crystal cell Clc connected to nth gate line and (n-1)th pre-stage gate line or between a liquid crystal cell Clc connected to nth gate line and a common storage line (not shown).
The data driving circuit 12 includes a plurality of data driving integrated circuits, each of which has a designated number of channels. Herein, the data driving integrated circuit includes a shift register for sampling a clock, a register for temperately storing data, a latch for storing the data by one line in response to a clock signal from the shift register and then simultaneously outputting the stored data corresponding to the one line, a digital to analog converter for selecting positive/negative gamma voltages corresponding to a value of the data from the latch, a multiplexer for selecting one of the data lines D1 to Dm to which an analog data (i.e., a video signal) converted by the positive/negative gamma voltage is applied, and an output buffer connected between the multiplexer and the selected data line. Such a data driving integrated circuit supplies the video signals to the data lines D1 to Dm under a control of the timing controller 11.
The gate driving circuit 13 includes a shift register for sequentially generating the scanning pulse, a level shifter for shifting a voltage of the scanning pulse to a voltage level suitable for driving the liquid crystal cell Clc. Such a gate driving circuit 13, under a control of the timing controller 11, supplies the scanning pulse sequentially synchronized with the video signal to the gate lines G1 to Gn.
The timing controller 11 employs vertical(V)/horizontal(H) signals and the clock(CLK) to generate a gate controlling signal (GDC) for controlling the gate driving circuit 13, and a data control signal (DDC) for controlling the data driving circuit 12. The DDC includes a source start pulse (SSP), a source shift clock (SSC), a source output enable (SOE), and a polarity signal (POL). The signal GDC includes a gate shift clock (GSC), a gate output signal (GOE) and a gate start pulse (GSP).
To drive the liquid crystal cell Clc in the liquid crystal display panel 14, the liquid crystal display device can employ an inversion driving method such as a frame inversion method, a line inversion method, a column inversion method, and/or a dot inversion method.
FIG. 2 represents a frame inversion method, FIG. 3 represents a line inversion method, FIG. 4 represents a column inversion method, FIG. 5 represents a one-dot inversion method, and FIG. 6 represents a two-dot inversion method. In FIGS. 2 to 6, (a) and (b) represents an inversion of a polarity of a video signal supplied every frame to a liquid crystal cells, ‘+’ represents a video signal of a positive polarity supplied to a liquid crystal cell, and ‘−’ represents a video signal of a negative polarity supplied to a liquid crystal cell.
However, such an inversion driving method has problems in that a current consumed by the device is raised due to an inversion of the video signal polarity and also a heat generated by the integrated circuit is raised. Especially, such above problems are deepened in the one-dot and the two-dot inversion driving method in which a polarity of a video signal is inverted every one horizontal interval or two horizontal interval. To solve such problems, a scheme reducing a voltage swing width by pre-charging the data lines D1 to Dm with aid of a charge sharing circuit has been suggested.
The charge sharing is perfectly performed in the data lines adjacent from the charge sharing circuit as shown in FIG. 7A. However the effect of the charge sharing is reduced as it becomes more distant from the charge sharing circuit by RC delay as shown in FIG. 7B. The decrease of the charge sharing effect becomes more apparent in a large-sized panel due to an increase of a load according to the large-sized scale.